1. Field of the Invention
The invention is related in general to a packaging integrated circuits, and in particular to a flip chip system with a hybrid underfill mixture that includes properties similar to a molecular level composition that does not interfere with solder interconnect formation.
2. Description of the Related Art
Flip chip technology is well known in the art for electrically connecting a die (hereinafter, a “chip” or “flip chip”) to a mounting substrate, such as a printed wiring board, or the like.
The active surface of the die is subject to numerous electrical couplings that are usually brought to the edge of the chip. Heat generation is significant at the active surface of the die, and consequently at the active surface of the chip. Electrical connections, referred variously to as balls, bumps, and others, are deposited as terminals on the active surface of a flip chip. The bumps include solders and/or plastics that make mechanical connections and electrical couplings to a substrate. The chip is inverted (hence, “flip chip”) onto a mounting substrate with the bumps aligned to bonding pads on the mounting substrate. If the bumps are solder bumps, the solder bumps on the flip chip are soldered to the bonding pads on the substrate. A gap exists between the flip chip active surface and the mounting substrate.
One electronic device includes a flip chip and mounting substrate, among other things. One characteristic of flip chip technology is shear stress on the solder joints during temperature cycling of the device. This shear stress is partially a result of a difference in the coefficients of thermal expansion (“CTE”) of the flip chip and the mounting substrate. Die materials such as silicon, germanium, and gallium arsenide, along with their packaging materials, may have CTEs in a range from about 3 ppm/° C. to about 6 ppm/° C. Mounting substrates are usually composites of organic-impregnated fiberglass dielectrics and metallic circuitry. These substrates may have CTEs in a range from about 15 ppm/° C. to about 25 ppm/° C. Consequently, a mismatch in the CTEs exists between the flip chip and the mounting substrate.
To reduce solder joint failures due to stress during thermal cycling, the solder joints are reinforced by filling the space between the flip chip and the mounting substrate, and around the solder joints, with an underfill composite. The two main processes that are commonly used to underfill the flip chip include the capillary underfill process and the no-flow underfill process.
A capillary underfill process typically proceeds by first aligning the solder bumps on a flip chip with the pads on a substrate and the solder is reflowed to form the solder joints. After forming the interconnect, the underfill is flowed between the flip chip and the mounting substrate. Thereafter, the underfill composite is cured. Capillary underfilling can be assisted by pumping the underfill composite between the flip chip and the mounting substrate, or by vacuum-assisted drawing the underfill composite between the flip chip and the mounting substrate.
The effectiveness of an underfill composite depends on its chemical, physical, and mechanical properties. Properties that make an underfill composite desirable include low CTE, low moisture uptake, high adhesion, high toughness, high glass transition (Tg) temperature, high heat distortion temperature, and others. The underfill composite includes particulate filler inorganics such as silica or the like, and metal flakes or the like. The particulate filler increases the modulus and acts as a CTE intermediary for the mismatched CTEs of flip chip and the mounting substrate. An example of a silica-filled composite is silica-filled, epoxy-based organics. However, the capillary underfill process that includes silica-filled composites or the like has technical challenges that are tedious, expensive, and sensitive to process rules and to chip size and shape. For example, particulate fillers in the underfill composite cause flowability to decrease between the flip chip active surface and the mounting substrate upper surface. Further, flow around the electrical bumps is also hindered by the increasingly smaller pitch and the increasingly smaller spacing between the flip chip and the mounting substrate.
In addition, the introduction of CTE-reducing filler particles in current underfill compositions of traditional flip chip packaging leads to a large viscosity increase, thus making it difficult for the underfill to flow by capillary forces. Furthermore, conventional flip chip packaging (with capillary flow underfill) is a costly multi-step and time consuming process which begins with solder reflow and interconnect formation, dispensing of the underfill and clean up of excess material, flow of underfill through capillary action and ends with curing of the underfill.
The no-flow underfill process avoids some challenges in the capillary flow underfill processes. In a no-flow underfill process, the underfill composite is dispensed on the mounting substrate or the flip chip, and the flip chip and the mounting substrate are brought into contact. The solder bumps on the chip and the pads on the substrate are aligned. Next, the underfill composite is cured prior to or substantially simultaneously with reflowing the solder to create the solder joints.
The no-flow underfill process also has technical challenges. The no-flow underfill material also must be made into a composite with the addition of a filler of silica or the like. Silica filler reduces the bump interconnection yield, because the filler gets deposited between the bumps and the pads such that electrical connections are not achieved.
Flip chip packaging with no-flow underfill is a much faster process than the capillary flow underfill process because solder interconnection and curing of the underfill occur simultaneously. However, a significant interconnection reliability problem is encountered due to the large concentration of filler necessary for the control of the CTE of the underfill. The interposition of these relatively large (microscale) filler particles between the solder bumps on the chip and the pads of the substrate during reflow gives rise to the interconnect reliability issues.